Hardened interlayer dielectric layer

ABSTRACT

The present disclosure relates to a semiconductor device and a manufacturing method thereof, and more particularly to an interlayer dielectric (ILD) layer in a semiconductor device. In one example, the ILD layer is over a substrate and includes a dielectric with a dielectric constant of less than about 3.3 and a hardness of at least about 3 GPa. The semiconductor device also includes an interconnect formed in the ILD layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.15/940,145, filed on Mar. 29, 2018 and titled “Hardened InterlayerDielectric Layer,” which claims the benefit of U.S. Provisional PatentApplication No. 62/564,460, filed on Sep. 28, 2017 and titled “HardenedInterlayer Dielectric Layer,” both of which are incorporated herein byreference in their entireties.

BACKGROUND

Semiconductor fabrication technologies can use dielectric materials asinsulating layers between circuits and components of circuits (e.g.,integrated circuits). For example, dielectric materials can be usedbetween interconnection layers of a multilayer interconnect structure ofa semiconductor device. These dielectric materials can be referred to as“interlayer dielectrics” (ILDs), also known as “inter-metal dielectrics(IMDs).” As dimensions decrease in semiconductor device components, therequirement to isolate adjacent features from one another becomes morecritical, and more difficult. The design of ILDs is thus critical tomeet these challenges.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the common practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofillustration and discussion.

FIG. 1 is a cross-sectional view of an exemplary semiconductor device,in accordance with some embodiments.

FIGS. 2A -2F are cross-sectional views of a partially-fabricatedexemplary semiconductor device, in accordance with some embodiments.

FIG. 3 illustrates exemplary occurrences of arcing in relation topressure and a ratio of radio frequency (RF) discharge power to flowrate in a chamber, in accordance with some embodiments.

FIG. 4 is a cross-sectional view of an exemplary apparatus for formingan interlayer dielectric (ILD) layer, in accordance with someembodiments.

FIG. 5 is a flow diagram of an exemplary method for forming asemiconductor device, in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over a second feature in the description that followsmay include embodiments in which the first and second features areformed in direct contact, and may also include embodiments in whichadditional features are disposed between the first and second features,such that the first and second features are not in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition does not in itselfdictate a relationship between the various embodiments and/orconfigurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper,” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The term “nominal” as used herein refers to a desired, or target, valueof a characteristic or parameter for a component or a process operation,set during the design phase of a product or a process, together with arange of values above and/or below the desired value. The range ofvalues can be due to slight variations in manufacturing processes ortolerances.

The term “vertical,” as used herein, means nominally perpendicular tothe surface of a substrate

The term “about” as used herein indicates the value of a given quantitythat can vary based on a particular technology node associated with thesubject semiconductor device. Based on the particular technology node,the term “about” can indicate a value of a given quantity that varieswithin, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% ofthe value).

Semiconductor chip fabrication process can be divided into three“modules,” in which each module may include all or some of the followingoperations: patterning (e.g., photolithography and etching),implantation, metal and dielectric material deposition, wet or drycleaning, and planarization (e.g., etch-back process or chemicalmechanical planarization). The three modules can be categorized as frontend of the line (FEOL), middle of the line (MOL)/middle end of the line(MEOL), and back end of the line (BEOL).

In the FEOL, active devices, such as field effect transistors (FETs),are formed. For example, FEOL includes the formation of source/drainterminals, a gate stack, and spacers on sides of the gate stack. Thesource/drain terminals can be doped substrate regions formed with animplantation process after the gate stack formation. The gate stack caninclude a metal gate electrode, which can include two or more metallayers. The gate dielectric can include a high dielectric constant(high-k) material (e.g., greater than 3.9, which is the dielectricconstant of silicon dioxide (SiO₂)). Metals in the gate electrode canset a work function of the gate, in which the work function can bedifferent between a p-type FET and an n-type FET. The gate dielectriccan provide electrical isolation between the metal gate electrode and achannel formed between the source and the drain terminals when the FETis in operation.

In the MOL, low level interconnects (contacts) are formed and caninclude two layers of contacts on top of each other. The MOLinterconnects can have smaller critical dimensions (CDs; e.g., linewidth) and can be spaced closer together compared to their BEOLcounterparts. A purpose of the MOL contact layers is to electricallyconnect the FET terminals (e.g., the source/drain and gate electrodes)to higher-level interconnects in BEOL. A first layer of contacts in MOL,known as “trench silicide (TS),” are formed over the source and drainterminals on either side of a gate stack. In the TS configuration, thesilicide is formed in the trench after trench formation. The silicidecan lower a resistance between source/drain regions and the metalcontacts. The gate stack and the first layer of contacts are consideredto be on the same “interconnect level.” The second layer of contacts canbe formed over the gate electrode and TS. MOL contacts can be embeddedin a dielectric material, or a dielectric stack of materials, whichensures their electrical isolation.

In the BEOL, an ILD layer is deposited over the MOL contacts. Asdisclosed herein, an “ILD layer” is also known as an “IMD layer.” Theformation of high level interconnects in the BEOL can include patterninga hard mask (HM) layer and subsequently etching through the HM layer toform holes and trenches in the ILD layer. The ILD layer can bemanufactured using a low-k material. Low-k materials can have adielectric constant below 3.9, which is the dielectric constant ofsilicon dioxide. Low-k materials in the BEOL include, for example,fluorine-doped silicon dioxide, carbon-doped silicon dioxide, or poroussilicon dioxide. These low-k materials can reduce unwanted parasiticcapacitances and minimize resistance-capacitance (RC) delays in the FET.BEOL interconnects can include two types of conductive lines: verticalinterconnect access lines (vias) and lateral lines (lines). The vias canrun through the ILD layer in a vertical direction and create electricalconnections to layers above or below the ILD layer. Lines can be laid inthe lateral direction within the ILD layer to connect a variety ofcomponents within the same ILD layer. The BEOL can include multiplelayers (e.g., up to 9 or more layers) of vias and lines with increasingCDs (e.g., line width) and interconnect pitch. Each layer can align to aprevious layer to ensure proper via and line connectivity.

Miniaturization of semiconductor devices (e.g., dimensional shrinkage inBEOL, such as the reduction of interconnect pitch) can decreasemechanical strength of low-k ILD layers. As a result, dielectric layerbending may occur during interconnect formation due to the weakmechanical strength of the low-k ILD layers. For example, stressintroduced by the deposition of a barrier layer may compromise thestructure of the low-k ILD layer surrounding a via such that thestructure may no longer support the via. Dielectric layer bending candecrease the CDs and cause poor metal gap-fill, thereby reducing yieldand reliability of semiconductor devices.

Various embodiments in accordance with the present disclosure providemechanisms of forming a low-k ILD layer high with improved hardness toincrease the mechanical strength in a semiconductor structure. Variouslow-k ILD layers can be fabricated for different interconnect pitches inthe BEOL. In some embodiments, for interconnect pitches less than 40 nm,a low-k ILD layer with enhanced hardness (e.g., at least 3 GPa) that issufficient to overcome dielectric layer bending can be employed. In someembodiments, by adjusting the ILD deposition parameters, e.g., the RFdischarge power and/or total gas flow rate, arcing occurred inplasma-enhanced processes can be prevented to avoid damaging thesemiconductor device when forming hardened ILD layers. As a result,semiconductor structures can be manufactures with lower RC delay, higherbreakdown resistance, and more controllable interconnect line structurein a fabrication process that minimizes dielectric layer arcing.

FIG. 1 is a cross-sectional view of an exemplary semiconductor device100, in accordance with some embodiments. Semiconductor device 100includes a substrate 102, a dielectric layer 104 on substrate 102, and acontact 106 in pre-metal dielectric layer 104. Substrate 102 may be adoped or undoped bulk silicon substrate or a silicon-on-insulator (SOI)substrate. The SOI substrate can include a layer of a semiconductormaterial such as silicon (Si), germanium (Ge), silicon germanium (SiGe),silicon germanium on insulator (SGOI), or combinations thereof. Othersubstrates that may be used include multi-layered substrates, gradientsubstrates, or hybrid orientation substrates.

In some embodiments, as part of the FEOL of semiconductor device 100,active devices (not shown), such as FETs, may be formed in and/or onsubstrate 102. The active devices may also include capacitors,resistors, inductors, or any other devices that can be used to generatethe desired structural and functional requirements of the design forsemiconductor device 100. The active devices may be formed using anysuitable methods either within or on the surface of substrate 102.

In some embodiments, pre-metal dielectric layer 104 is disposed onsubstrate 102. Dielectric layer 104 may include a dielectric, such assilicon dioxide, or a dielectric stack, which ensures electricalisolation. As part of the MOL of semiconductor device 100, contact 106is formed in dielectric layer 104 to electrically connect the activedevices in and/or on substrate 102. Contact 106 may include conductivematerials, such as tungsten (W). In some embodiments, contact 106 mayfurther include a barrier layer and an adhesion layer (not shown) toprevent diffusion and provide adhesion of the conductive material ofcontact 106 to dielectric layer 104. The barrier layer may be made ofone or more layers of titanium (Ti), titanium nitride (TiN), tantalum(Ta), tantalum nitride (TaN), or any other suitable materials.

In some embodiments, the BEOL of semiconductor device 100 includes afirst etch stop layer 108, a first ILD layer 110 on first etch stoplayer 108, interconnects 112, 114 in first ILD layer 110, a second etchstop layer 116 on first ILD layer 110, and a second ILD layer 118 onsecond etch stop layer 116. First etch stop layer 108 may be used toprotect substrate 102, dielectric layer 104, and contact 106 from damagecaused by further processing and provide a control point for furtheretching processes. In some embodiments, first etch stop layer 108 may bemade of silicon nitride using plasma enhanced chemical vapor deposition(PECVD). Other materials, such as nitride, oxynitride, carbide, boride,combinations thereof, or the like can be used to form first etch stoplayer 108 and alternative techniques of forming first etch stop layer108 can be used such as low pressure CVD (LPCVD), physical vapordeposition (PVD), or the like. First etch stop layer 108 may have athickness of between about 50 Å and about 2,000 Å, such as about 200 Å.

In some embodiments, first ILD layer 110 is disposed on first etch stoplayer 108, and over substrate 102. First ILD layer 110 includes a firstdielectric having a dielectric constant of less than about 3.3 and ahardness greater than 3 GPa. In some embodiments, the first dielectrichas a dielectric constant of about 3 (e.g., 3) and a hardness of about 5GPa (e.g., 5 GPa). The dielectric constant of the first dielectric ismeasured by a mercury probe approach. In some embodiments, thedielectric constant of the first dielectric is between about 2.9 andabout 3.3 (e.g., between 2.9 and 3.3). In some embodiments, thedielectric constant of the first dielectric is between about 2.9 andabout 3.2 (e.g., between 2.9 and 3.2, between 2.9 and 3.1, between 2.9and 3.0, between 3.0 and 3.2, between 3.0 and 3.1, or between 3.1 and3.2). The first dielectric can be a low-k dielectric as it has adielectric constant less than 3.9. The hardness of the first dielectriccan be measured by a nanoindenter approach. In some embodiments, thehardness of the first dielectric is between about 3 GPa and about 7 GPa(e.g., between 3 GPa and 7 GPa, between 4 GPa and 7 GPa, between 5 GPaand 7 GPa, between 6 GPa and 7 GPa, between 3 GPa and 6 GPa, between 4GPa and 6 GPa, between 5 GPa and 6 GPa, between 3 GPa and 5 GPa, between4 GPa and 5 GPa, or between 3 GPa and 4 GPa). In some embodiments, thefirst dielectric is considered as an enhanced hardness dielectric as ithas a hardness greater than about 3 GPa.

In some embodiments, the first dielectric of first ILD layer 110 has arefractive index of at least about 1.42 for light having a wavelength of633 nm. The refractive index of the first dielectric is measured by anellipsometer approach. In some embodiments, the refractive index of thefirst dielectric is between about 1.42 and about 1.48 (e.g., between1.42 and 1.48) for light having a wavelength of 633 nm. In someembodiments, the first dielectric of first ILD layer 110 has a densityof at least 1.6 g/cm³. The density of the first dielectric is measuredby an X-ray reflectometry approach. In some embodiments, the density ofthe first dielectric is between about 1.6 g/cm³ and about 1.9 g/cm³(e.g., between 1.6 g/cm³ and 1.9 g/cm³). The first dielectric of firstILD layer 110 may be made of, for example, fluorine-doped silicondioxide, carbon-doped silicon dioxide, porous silicon dioxide, porouscarbon-doped silicon dioxide, spin-on organic polymeric dielectrics,spin-on silicon based polymeric dielectrics, or the like.

In some embodiments, a plurality of interconnects, including a via 112and a line 114, are formed in first ILD layer 110. Via 112 may be formedin first ILD layer 110 and first etch stop layer 108 to electricallyconnect contact 106 in dielectric layer 104 to form a multilayerinterconnect structure in semiconductor device 100. Line 114 may beformed in first ILD layer 110. Via 112 and line 114 may includeconductive materials, such as copper (Cu). In some embodiments, via 112and line 114 may further include barrier layers and/or adhesion layers(not shown) to prevent diffusion and provide adhesion of the conductivematerials of via 112 and line 114 to the first dielectric of first ILDlayer 110. The barrier layer may be made of one or more layers oftitanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride(TaN), or any other suitable materials.

In some embodiments, a pitch of the plurality of interconnects (e.g.,via 112 and line 114) in first ILD layer 110 is less than about 40 nm(e.g., less than 40 nm, between 1 nm and 40 nm, between 5 nm and 40 nm,between 10 nm and 40 nm, between 15 nm and 40 nm, between 20 nm and 40nm, between 25 nm and 40 nm, or between 30 nm and 40 nm). In someembodiments, the pitch of the plurality of interconnects in first ILDlayer 110 is between about 28 nm and about 39 nm (e.g., between 28 nmand 39 nm). In some embodiments, the pitch of the plurality ofinterconnects in first ILD layer 110 is about 28 nm (e.g., 28 nm), about20 nm (e.g., 20 nm), about 16 nm (e.g., 16 nm), about 12 nm (e.g., 12nm), about 10 nm (e.g., 10 nm), about 7 nm (e.g., 7 nm), about 5 nm(e.g., 5 nm), or about 3 nm (e.g., 3 nm). It is to be appreciated thatthe occurrence of dielectric layer bending may relate to theinterconnect pitch since smaller interconnect pitches may require ahigher dielectric hardness to support the interconnect openings prior togap-fill. Thus, the hardness (and the dielectric constant in someembodiments) of the first dielectric of first ILD layer 110 may varydepending on the pitch of the interconnects in first ILD layer 110. Insome embodiments, the first dielectric having a hardness of at leastabout 3 GPa can reduce dielectric layer bending for interconnects havinga pitch of about 40 nm. In some embodiments, when the pitch of theinterconnects in first ILD layer 110 is between 28 nm and 39 nm, thespacing of the first dielectric in first ILD layer 110 is between 14 nmand 20 nm, and the aspect ratio of the first dielectric in first ILDlayer 110 is 3.8. Further, in some embodiments, the dielectric constantof the first dielectric is between 2.9 and 3.2, and the hardness of thefirst dielectric is between 3 GPa and 7 GPa.

In some embodiments, second etch stop layer 116 is formed on first ILDlayer 110 to protect first ILD layer 110 and via 112 and line 114 fromdamage caused by further processing and provide for a control point forfurther etching processes. In some embodiments, second etch stop layer116 may be made of silicon nitride, oxynitride, carbide, boride,combinations thereof, or the like. Second etch stop layer 116 may have athickness of between about 50 Å and about 2,000 Å, such as about 200 Å.

In some embodiments, second ILD layer 118 is disposed on second etchstop layer 116. Similar to first ILD layer 110, second ILD layer 118 mayinclude an enhanced hardness, low-k dielectric as described herein withrespect to the first dielectric. The material properties of seconddielectric in second ILD layer 118 may be nominally the same as thematerial properties of first dielectric in first ILD layer 110,according to some embodiments. For example, the dielectric constant andhardness of the first and second dielectrics in first and second ILDlayers 110 and 118, respectively, may be nominally the same.

In some embodiments, the material properties of second dielectric insecond ILD layer 118 may be different than the material properties offirst dielectric in first ILD layer 110, according to some embodimentsFor example, the pitches of the interconnects in first and second ILDlayers 110 and 118 can be different since first and second ILD layers110 and 118 are in different vertical levels of semiconductor device100. The pitch of the interconnects (not shown) in second ILD layer 118can be larger than the pitch of the interconnects in first ILD layer110. Thus, the hardness of the second dielectric in second ILD layers118 may be smaller than the hardness of the first dielectric in firstILD layer 110. In another example, the dielectric constants of the firstand second dielectrics in first and second ILD layers 110 and 118 may bedifferent, and/or the hardnesses of the first and second dielectrics infirst and second ILD layers 110, 118 may be different.

FIGS. 2A-2F are cross-sectional views of a partially-fabricatedexemplary semiconductor device 200, in accordance with some embodiments.In FIG. 2A, a partially-fabricated semiconductor device 200 includesfirst etch stop layer 108 and first ILD layer 110 over a substrate (notshown). A photolithography operation and a series of etching operationscan be performed to form openings for interconnects in first etch stoplayer 108 and first ILD layer 110. An HM layer 202 is deposited on firstILD layer 110, followed by photoresist 204 coated on HM layer 202. HMlayer 202 may include a metal film, such as but not limited to, chrome(Cr) or titanium nitride (TiN).

As described herein with respect to FIG. 1, first ILD layer 110 includesthe first dielectric having a dielectric constant of at most about 3.3and a hardness of at least about 3 GPa, according to some embodiments.The first dielectric may be formed by a film deposition process, such asa CVD process, using precursor and oxygen (O₂) gas. The precursorincludes, for example, tetra-ethyl-ortho-silicate (TEOS), methyldiethoxysilane (DEMS), silanes, alkylsilanes (e.g., trimethylsilane andtetramethylsilane), alkoxysilanes (e.g., methyltriethoxysilane (MTEOS),methyltrimethoxysilane (MTMOS), methyldimethoxysilane (MDMOS),trimethylmethoxysilane (TMMOS) and dimethyldimethoxysilane (DMDMOS)),linear siloxanes and cyclic siloxanes (e.g.,octamethylcyclotetrasiloxane (OMCTS) and tetramethylcyclotetrasiloxane(TMCTS)), or any combination thereof. In some embodiments, CxHy isincorporated within precursor (e.g., TEOS), or CxHy is added by separateprecursor (e.g., C₃H₈ or atom-transfer radical-polymerization (ATRP))during the CVD process. In one example, the precursor includestrimethylsilane (3MS)/tetramethysilane (4MS) (Si—(CxHy)z; x=1˜10,y=2˜30, z=1˜4 or O embedded). In another example, the precursor includesSi—O embedded TEOS/mDEOS. In still another example, the precursorincludes Si—C—Si embedded bis(triethoxysilyl)ethane (BTSE). In someembodiments, porogen is not used in the CVD process. In someembodiments, a PECVD process is used to deposit the first dielectric toincrease the deposition rate of the CVD process. It is to be appreciatedthat the film deposition process for forming the first dielectric can beany other suitable process such as, for example, atomic layer deposition(ALD), plasma-enhanced ALD (PEALD), electron beam assisted deposition,molecular beam epitaxy (MBE), high density plasma CVD (HDPCVD), metalorganic CVD (MOCVD), remote plasma CVD (RPCVD), plating, and/orcombinations thereof.

In some embodiments, the first dielectric of first ILD layer 110 isdeposited using PECVD. The temperature in the PECVD chamber duringdeposition may be between about 100° C. and about 500° C. (e.g., between100° C. and 500° C.). To control the hardness of the first dielectric tobe at least 3, in the PECVD chamber, the ratio (flow ratio) of the firstflow rate of the precursor and the second flow rate of the oxygen gas isat least about 25 (e.g., 25). In some embodiments, the flow ratio isbetween about 25 and about 100 (e.g., between 25 and 100, 35 and 100, 45and 100, 55 and 100, 65 and 100, 75 and 100, 85 and 100, 95 and 100, 25and 90, 35 and 90, 45 and 90, 55 and 90, 65 and 90, 75 and 90, 85 and90, 25 and 80, 35 and 80, 45 and 80, 55 and 80, 65 and 80, 75 and 80, 25and 70, 35 and 70, 45 and 70, 55 and 70, 65 and 70, 25 and 60, 35 and60, 45 and 60, 55 and 60, 25 and 50, 35 and 50, 45 and 50, 25 and 40, 35and 40, or 25 and 30). In some embodiments, the gas ratio is about 50(e.g., 50).

In some embodiments, increasing the flow ratio (e.g., above 25) mayincrease the occurrence of arcing occurred during the PECVD process. Insome embodiments, to decrease the occurrence of arcing in depositing thefirst dielectric of first ILD layer 110, the power of the RF dischargeis at most about 600 W. In some embodiments, the RF discharge power isbetween about 200 W and about 600 W (e.g., between 200 W and 600 W, 300W and 600 W, 400 W and 600W, 500 W and 600 W, 200 W and 500 W, 300 W and500 W, 400 W and 500 W, 200 W and 400 W, 300 W and 400 W, or 200 W and300 W). In some embodiments, to decrease the occurrence of arcing indepositing the first dielectric of first ILD layer 110, the total flowrate of the first flow rate of the precursor and the second flow rate ofthe oxygen gas is at most about 5000 sccm. In some embodiments, thetotal flow rate is between about 1500 sccm and about 5000 sccm (e.g.,between 1500 sccm and 5000 sccm, 2500 sccm and 5000 sccm, 3500 sccm and5000 sccm, 4500 sccm and 5000 sccm, 1500 sccm and 4000 sccm, 2500 sccmand 4000 sccm, 3500 sccm and 4000 sccm, 1500 sccm and 3000 sccm, 2500sccm and 3000 sccm, or 1500 sccm and 2000 sccm).

In some embodiments, ultraviolet (LTV) curing is performed with UVwavelength at 150 nm to 400 nm, with a pressure of 1 Torr to 50 Torr,with a temperature of 100° C. to 500° C., and with an environment ofhelium (He), argon (Ar), nitrogen (N₂), and/or hydrogen (H₂) gases. Insome embodiments, after depositing the first dielectric, a thermaltreatment and a plasma treatment are also performed at a temperaturebetween 100° C. and 500° C. and in an environment of helium (He), argon(Ar), nitrogen (N₂), hydrogen (H₂), carbon monoxide (CO), carbon dioxide(CO₂), and/or nitrous oxide (N₂O) gases. In some embodiments, afterdepositing the first dielectric, an electron beam treatment is performedat a temperature of 100° C. to 500° C., with a pressure of 0.01 mTorr to100 mTorr, and in an environment of helium (He), argon (Ar), nitrogen(N₂), hydrogen (H₂), carbon monoxide (CO), carbon dioxide (CO₂), and/ornitrous oxide (N₂O) gases.

In FIG. 2B, photoresist 204 is photo-exposed and patterned over HM layer202 to form a patterned photoresist 206. Patterned photoresist 206 canbe used to expose areas of partially-fabricated semiconductor device 200where interconnects will be formed and to protect other areas whereinterconnects should not be formed. The photolithography mask for makingpatterned photoresist 206 may have a pitch that is nominally the same asthe pitch of the interconnects to be formed in first ILD layer 110 ofpartially-fabricated semiconductor device 200. That is, in someembodiments, the pitch of the interconnects to be formed in first ILDlayer 110 of partially-fabricated semiconductor device 200 may bedefined by the pitch of patterned photoresist 206.

In FIG. 2C, HM layer 202 is etched using patterned photoresist 206 asthe mask to form a patterned HM layer 208. The exposed areas of HM layer202 that are not covered by patterned photoresist 206 are removed by awet etching or a dry etching process, leaving the areas of HM layer 202that are covered by patterned photoresist 206 remain in patterned HMlayer 208. The etching processes can be performed using dry etchingprocesses, such as reactive ion etch (RIE) or other suitable processes.In some embodiments, the etching processes can be formed using wetchemical etching process.

Another etching process using patterned HM layer 208 as the mask removesexposed areas of first ILD layer 110 and first etch stop layer 108 toform a via hole 210 that stops on underlying contact (not shown). Theetching process also removes the exposed areas of first ILD layer 110 toform a trench 212 that stops in first ILD layer 110. In someembodiments, the etching process has high selectivity for first ILDlayer 110 and first etch stop layer 108. In some embodiments, theetching process automatically stops after a predetermined amount oftime, for example, for forming trench 212. An etching process which isterminated after a predetermined amount of time is referred to as a“timed etch.” An “end-pointed” etching process is a process thatautomatically stops when the layer directly underneath the etched layeris detected, for example, for forming via hole 210. End-point detectionis possible because first etch stop layer 108 and the underlying layercontact are made of different materials. Consequently, first etch stoplayer 108 and the underlying layer can have different etch rates for agiven etching chemical substance. Since the etching process can be usedto etch different materials (e.g., first ILD layer 110 and first etchstop layer 108), different etching chemical substances may be required.An exemplary etching chemical substance can include a combination ofhydrobromic acid (HBr), helium (He), oxygen (O₂) and chlorine (Cl₂). Inaddition to the etching chemical substance, other etching processparameters can be adjusted, such as flow rate, temperature, andpressure. These parameters can be used to control the etch rate, etchprofile, uniformity, etc.

In FIG. 2D, a gap-fill process is performed to fill via hole 210 andtrench 212 with conductive material 216. Prior to a deposition ofconductive material 216, a barrier layer 214 is first deposited to coverthe field regions of partially-fabricated semiconductor device 200, thesidewalls of via hole 210 and trench 212, and the bottom surface oftrench 212. Barrier layer 214 may be made of one or more layers oftitanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride(TaN), or any other suitable materials by CVD and/or PVD. Conductivematerial 216, such as copper (Cu), cobalt (Co), aluminum (Al), graphene,or any other suitable conductive material, may be deposited over barrierlayer 214. Conductive material 216 may be deposited by CVD, PVD, anelectroplating process, an electroless process, or any other suitabledeposition process. Depending on the material of conductive material216, a seed layer (now shown) may be deposited over barrier layer 214prior to the deposition of conductive material 216.

In FIG. 2E, conductive material 216 is removed to a depth that reachesor approximately reaches the top surface of first ILD layer 110.Patterned photoresist 206 and patterned HM layer 208 may be removed toexpose first ILD layer 110. In some embodiments, patterned photoresist206 and/or patterned HM layer 208 may be removed prior to the formationof barrier layer 214. Conductive material 216, patterned photoresist206, and patterned HM layer 208 can be removed by chemical mechanicalpolishing (CMP), dry etching, wet etching, or any other suitable removaltechnique.

In FIG. 2F, second etch stop layer 116 is deposited on first ILD layer110, and second ILD layer 118 is deposited on second etch stop layer 116and formed over first ILD layer 110. The process of forming second etchstop layer 116 may be nominally the same as the process of forming firstetch stop layer 108. Second ILD layer 118 includes the seconddielectric. In some embodiments, the process of forming second ILD layer118 may be nominally the same as the process of forming first ILD layer110 such that the material properties (e.g., dielectric constant andhardness) of the second dielectric of second ILD layer 118 are nominallythe same as those of the first dielectric of first ILD layer 110 asdescribed herein in detail.

In some embodiments, depending on the pitch of the interconnects to beformed in second ILD layer 118, the process of forming second ILD layer118 may be different than the process of forming first ILD layer 110such that the material properties (e.g., dielectric constant andhardness) of the second dielectric of second ILD layer 118 are differentfrom those of the first dielectric of first ILD layer 110. For example,the second dielectric may be different than the first dielectric andhave a dielectric constant of at most about 3.3 and a hardness of atleast about 3 GPa. In some embodiments, the hardness of the seconddielectric of second ILD layer 118 is less than the hardness of thefirst dielectric of first ILD layer 110. In some embodiments, the seconddielectric of second ILD layer 118 may have a hardness less than 3 GPa(which may not be an enhanced hardness dielectric according toembodiments of the present disclosure).

FIG. 3 illustrates exemplary occurrences of arcing in relation to thepressure and the ratio of RF discharge power and flow rate in thechamber, in accordance with some embodiments. In FIG. 3, each solid dotrepresents one deposition event in which arcing occurs, and each opendot represents one deposition event in which no arcing occurs. A “arcingzone” can be seen in FIG. 3 (represented as the hashed region), whilethe remaining region is a “non-arcing zone.” In some embodiments,increasing the deposition pressure and/or decreasing the ratio of RFdischarge power and flow rate may move the deposition events out fromthe arcing zone in FIG. 3.

FIG. 4 is a cross-sectional view of an exemplary apparatus 400 forforming an ILD layer, in accordance with some embodiments. Apparatus 400may be used to deposit an enhanced hardness low-k dielectric in an ILDlayer, such as first ILD layer 110 and second ILD layer 118 as describedherein. Apparatus 400 may be a CVD machine (e.g., a PECVD machine), anALD machine (e.g., a PEALD machine), an electron beam assisteddeposition machine, or any other suitable machine for film deposition.Apparatus 400 may include a chamber 401, a gas input area 403, and acontroller 405. Chamber 401 may be capable of maintaining a vacuum,holding substrate 102 (and its overlying layers such as dielectric layer104 and first etch stop layer 108) on a platen 407, and exhausting gasesthrough exhaust ports 409. Further, a showerhead 411 is disposed withinchamber 401. Showerhead 411 may be connected to gas input area 403,which feeds gas into showerhead 411. Showerhead 411 may receive multiplegases simultaneously from gas input area 403 through gas pipes 415.Mechanisms 417 may be in place to structurally support, heat, and rotatesubstrate 102. In some embodiments, chamber 401 may be configured tohold multiple work pieces.

Gas input area 403 may be internal to apparatus 400, such as bottles ofsource gas (e.g., precursors and oxygen gas as described herein),alternate gas sources, a valve system connected to an external gasdistribution area, or the like. Alternately, gas input area 403 may beexternal to apparatus 400. Multiple gases may be received by showerhead411, which delivers the gases to chamber 401.

Controller 405 may be any appropriate microprocessor unit, including acomputer internal or external to apparatus 400. Controller 405 maycontrol the gas flow into showerhead 411 through a connection 419.Further, controller 405 may control the temperature, the rotation ofsubstrate 102, the vacuum and/or pumping of chamber 401, and the like,through a connection 421.

In some embodiments, apparatus 400 is a PECVD machine, a PEALD machine,or any plasma-enhanced deposition machine. Apparatus 400 can include anRF source 413 for generating plasma in chamber 401 during thedeposition. Controller 405 may further control the power of RF dischargegenerated by RF source 413 during the deposition.

In some embodiments, controller 405 controls gas input area 403 tointroduce the precursor and the oxygen gas (e.g., at the same time) tochamber 401. For example, the precursor may be introduced at a rate ofbetween about 1440 sccm and about 4950 sccm, such as about 2942 sccm,while the oxygen gas may be introduced at a rate of between about 50sccm and about 60 sccm, such as about 58 sccm. In some embodiments,controller 405 controls gas input area 403 so that the total flow rateof the precursor and the oxygen gas is between 1500 sccm and 5000 sccm,such as 3000 sccm, and the flow ratio of the precursor and the oxygengas is between 25 and 100, such as 50. In some embodiments, controller405 controls RF source 413 to generate plasma at the RF discharge powerof between 200 W and 600 W, such as 400 W.

FIG. 5 is a flow diagram of an exemplary method 500 of forming asemiconductor device, in accordance with some embodiments. Otheroperations may be performed between the various operations of method500, and are omitted merely for clarity. The fabrication process of asemiconductor device having an ILD layer including an enhanced hardnesslow-k dielectric is not limited to the exemplary method 500.

Method 500 starts with operation 502, where a substrate is provided. Thesubstrate may be a doped or undoped bulk silicon substrate or a SOIsubstrate. For example, as shown in FIG. 1, FEOL and MOL structures,such as the active devices, dielectric layer 104, and contact 106 may beformed over substrate 102. First etch stop layer 108 may be formed oversubstrate 102 as well.

Method 500 continues with operation 504, where a first ILD layer isdeposited over the substrate. The first ILD layer may include adielectric made of carbon-doped silicon dioxide. The dielectric constantof the dielectric is at most about 3.3, and the hardness of thedielectric is at least about 3 GPa, according to some embodiments. Insome embodiments, the dielectric constant of the dielectric is betweenabout 2.9 and about 3.2, such as about 3. In some embodiments, thehardness of the dielectric is between about 3 GPa and about 7 GPa, suchas about 5 GPa. In some embodiments, the refractive index of thedielectric is at least about 1.42 for light having a wavelength of 633nm, such as between about 1.42 and about 1.48. In some embodiments, thedensity of the dielectric is at least about 1.6 g/cm³, such as about 1.6g/cm³ and about 1.9 g/cm³. For example, the first ILD layer may be firstILD layer 110 or second ILD layer 118 in FIG. 1.

In some embodiments, operation 504 may include two operations fordepositing the first ILD layer. First, a precursor and oxygen gas areintroduced to a deposition chamber (e.g., chamber 401). A ratio betweenthe first flow rate of the precursor and the second flow rate of theoxygen gas is at least about 25, and a total flow rate of the first andsecond flow rates is at most about 5000 sccm. In some embodiments, theratio is between about 25 and about 100, and the total flow rate isbetween about 1500 sccm and about 5000 sccm. The temperature in thechamber is between about 100° C. and about 500° C. For example, as shownin FIG. 4, controller 405 controls gas input area 403 to introduce theprecursor and the oxygen gas at the same time to chamber 401. Controller405 may also control the flow ratio and total flow rate as describedherein.

Second, an RF discharge having a power of at most 600 W is provided. Insome embodiments, the power of the RF discharge is between about 200 Wand about 600 W. For example, as shown in FIG. 4, controller 405controls RF source 413 to provide RF discharge at the power as describedherein to generate plasma in chamber 401 during the deposition of theenhanced hardness low-k dielectric of the first ILD layer. Bycontrolling the total flow rate and/or the RF discharge power asdescribed herein, the chance of arcing occurred during operations inmethod 600 can be reduced or eliminated.

Method 500 continues with operation 506, where opening are etched in thefirst ILD layer. Openings may include via openings and trenches and maybe etched through the entire thickness of the first ILD layer or some ofthe entire thickness of the first ILD layer.

Method 500 continues with operation 508, where interconnects aredeposited in the openings. The pitch of the interconnects may be at mostabout 40 nm. In some embodiments, the pitch of the interconnects isbetween about 28 nm and about 39 nm, such as about 28 nm. For example,the interconnects may include via 112 and line 114 in FIG. 1.

Method 500 continues with operation 510 where a second ILD layer isdeposited over the first ILD layer. In some embodiments, the second ILDlayer includes a second dielectric having a dielectric constantdifferent from the dielectric constant of the first dielectric of thefirst ILD layer and a hardness different from the hardness of the firstdielectric of the first ILD layer. In some embodiments, the second ILDlayer includes a second dielectric having a dielectric constantnominally the same as the dielectric constant of the first dielectric ofthe first ILD layer and a hardness nominally the same as the hardness ofthe first dielectric of the first ILD layer.

According to some embodiments, an enhanced hardness low-k dielectric inILD layers as disclosed in the present disclosure can reduce oreliminate dielectric layer bending in the openings. Via bending is oneexample of dielectric layer bending in openings, which is the bending ofsidewalls of an opening (e.g., a trench) in the ILD layer induced by thevia underneath. Via bending can cause the critical dimension (CD) of aninterconnect formed in the trench to change, which can be quantified byAfter Barrier Seed Deposition Inspection (ABSI) CD bias. In someembodiments, an enhanced hardness low-k dielectric in ILD layers asdisclosed herein can cause the ABSI CD bias of interconnects formed inthe ILD layers to be less than about 3 nm, such as less than 0.1 nm,less than 0.2 nm, less than 0.3 nm, less than 0.4 nm, less than 0.5 nm,less than 0.6 nm, less than 0.7 nm, less than 0.8 nm, less than 0.9 nm,less than 1 nm, less than 1.5 nm, less than 2 nm, less than 2.5 nm, lessthan 3 nm, any range bounded on the lower end by any of these values, orwithin any range defined by any two of these values.

Various embodiments in accordance with the present disclosure providemechanisms of forming an enhanced hardness low-k dielectric in ILDlayers to increase the mechanical strength in a semiconductor structure.In some embodiments, an ILD layer having an enhanced hardness low-kdielectric is formed. The hardness of the low-k dielectric is sufficientto overcome the dielectric layer bending of the openings (e.g., trenchesand via holes) of the interconnects (e.g., lines and vias) formed in theILD layer. In some embodiments, the low-k ILD layers with enhancedhardness may be formed by a high-carbon deposition process. For example,the ratio between the flow rate of the precursor and the flow rate ofthe oxygen gas introduced into the deposition chamber may be at leastabout 25. In some embodiments, by adjusting the ILD depositionparameters, e.g., the RF discharge power and total flow rate, arcingoccurred in some plasma enhanced processes can be prevented to avoiddamaging the semiconductor devices during the high-carbon depositionprocess.

In some embodiments, a semiconductor device includes a substrate and aILD layer over the substrate. The ILD layer includes a dielectric with adielectric constant of less than about 3.3 and a hardness of at leastabout 3 GPa. The semiconductor device also includes an interconnectformed in the ILD layer.

In some embodiments, a method of forming a semiconductor device includesproviding a substrate and depositing an ILD layer over the substrate.The ILD layer includes a dielectric with a dielectric constant of lessthan about 3.3 and a hardness of at least about 3 GPa. The methodfurther includes etching an opening in the ILD layer and depositing aninterconnect in the opening.

In some embodiments, a method of forming a semiconductor device includesproviding a substrate and depositing an ILD layer over the substrate.Forming the ILD layer includes introducing a precursor at a first flowrate and an oxygen gas at a second flow rate to the chamber. A ratiobetween the first flow rate and the second flow rate is at least about25. A total flow rate of the first and second flow rates is at mostabout 5000 sccm. Forming the ILD layer further includes providing an RFdischarge having a power of at most about 600 W in the chamber. Themethod further includes etching an opening in first ILD layer anddepositing an interconnect in the opening.

It is to be appreciated that the Detailed Description section, and notthe Abstract of the Disclosure, is intended to be used to interpret theclaims. The Abstract of the Disclosure section may set forth one or morebut not all exemplary embodiments contemplated and thus, are notintended to be limiting to the subjoined claims.

The foregoing disclosure outlines features of several embodiments sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art will appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodimentsintroduced herein. Those skilled in the art will also realize that suchequivalent constructions do not depart from the spirit and scope of thepresent disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the subjoined claims.

What is claimed is:
 1. A device, comprising: a substrate; a firstinterlayer dielectric (ILD) layer over the substrate, wherein the firstILD layer comprises a first dielectric having a dielectric constant lessthan about 3.3 and a hardness of at least about 3 GPa; and aninterconnect formed in the first ILD layer, the interconnect having apitch less than about 40 nm.
 2. The device of claim 1, wherein arefractive index of the first ILD layer is at least about 1.42 for lighthaving a wavelength of 633 nm.
 3. The device of claim 1, wherein adensity of the first ILD is at least about 1.6 g/cm³.
 4. The device ofclaim 1 wherein the first ILD layer comprises a porous, carbon-dopedmaterial.
 5. The device of claim 1, further comprising a second ILDlayer above the first ILD layer.
 6. The device of claim 5, furthercomprising an etch stop layer between the first ILD layer and the secondILD layer.
 7. The device of claim 5, wherein: the second ILD layer has adielectric constant substantially equal to that of the first ILD layer;and the second ILD layer has a hardness substantially equal to that ofthe first ILD layer.
 8. The device of claim 5, wherein: the second ILDlayer has a dielectric constant different from that of the first ILDlayer; and the second ILD layer has a hardness different from that ofthe first ILD layer.
 9. The device of claim 1, wherein the dielectricconstant of the first ILD layer is about 3.0 and the hardness of thefirst ILD layer is about 5 GPa.
 10. The device of claim 1, wherein acritical dimension (CD) bias of the interconnect formed in the first ILDlayer is less about 3 nm.
 11. A semiconductor device, comprising: asemiconductor substrate; a first interlayer dielectric (ILD) layer onthe substrate, the first ILD layer having a hardness of at least about3.2 GPa; vias and metal lines in the first ILD layer, the vias having avia pitch and the metal lines having a metal line pitch; and a secondILD layer over the first ILD layer, the second ILD layer havinginterconnects with an interconnect pitch that greater than the via pitchand the metal line pitch.
 12. The semiconductor device of claim 11,wherein the hardness of the first ILD layer is between about 3.2 GPa andabout 7 GPa.
 13. The semiconductor device of claim 11, wherein adielectric constant of the first ILD layer is between about 2.9 andabout 3.2.
 14. The semiconductor device of claim 11, wherein arefractive index of the first ILD layer is between about 1.42 and about1.48.
 15. The semiconductor device of claim 11, wherein a density of thefirst ILD layer is between about 1.6 g/cm³ and about 1.9 g/cm³.
 16. Thesemiconductor device of claim 11, wherein the interconnect pitch isbetween about 28 nm and about 39 nm.
 17. A device, comprising: asubstrate; a porous carbon-doped interlayer dielectric (ILD) layer abovethe substrate, the porous carbon-doped ILD layer having a hardnessgreater than about 3 GPa; a first plurality of interconnects formed inthe porous carbon-doped ILD layer, the first plurality of interconnectshaving a first pitch less than about 40 nm; a second ILD layer above thefirst plurality of interconnects; and a second plurality ofinterconnects formed in the second ILD layer, the second plurality ofinterconnects having a second pitch greater than the first pitch. 18.The device of claim 17, wherein the substrate comprises transistors inelectrical contact with the first and second pluralities ofinterconnects.
 19. The device of claim 17, wherein the substratecomprises an etch stop layer under the porous carbon-doped ILD layer.20. The device of claim 19, wherein the first plurality of interconnectscomprise vias that extend through the etch stop layer and, adjacent tothe vias, metal lines that do not extend through the etch stop layer.